The present invention relates to a cleaning method and a cleaning device and a cleaning tool for board electrical-test probes, and more specifically, to a technology for removing the dirt deposited to the extreme ends of the contact pins, which come into direct contact with the conductor patterns on a printed circuit board, of the electrical-test probes used in a test device which is used to test the electrically mounted state of electronic parts such as, for example, ICs, resistors, capacitors and the like of the printed circuit board after they are soldered thereon.
Conventionally, a surface mount technology of electronic parts to a printed circuit board includes a so-called STM method of reflow soldering electronic parts by printing cream solder and a soldering method of blowing solder to the printed circuit board on which electronic parts are mounted using a solder flow vessel. However, any of the methods employs chlorofluorocarbon or 1,1,1-trichloroethane to wash and remove solder flux used in the soldering from the surface where the electric parts are soldered.
However, it is found that a reason for causing the recent environmental pollution attributes to the use of chlorofluorocarbon or 1,1,1-trichloroethane, thus requiring the use of it to be refrained. To cope with this problem, the improvement of the physical property and corrosiveness of the flux is proceeded to make it unnecessary to wash it. Further, manufacturers positively struggle to use a cleaning agent which causes no environmental pollution or makes the cleaning and removal of the flux with water.
However, since it is conceived that the use of the cleaning agent or water may cause different environmental pollution, a best way at present is to make the cleaning of the flux unnecessary, which is also favorable from the viewpoint of cost reduction.
However, there is known a problem that when the flux is not cleaned, since it is deposited to the contact pins used in an electrical test performed after soldering and gradually grown, conductivity failure may be caused in the electrical test.
FIG. 19 is a flowchart for mounting electronic parts on a printed circuit board and shows steps for mounting the parts on the printed circuit board 30 and shipping it.
In the drawing, a printed circuit board 30 is prepared at step S1 and cream solder is printed at step S2. Thereafter, surface mounting electronic parts 31 are mounted by a mounter or the like and reflow soldering is carried out at step S4. Thereafter, an incircuit test is effected at next step S5 without cleaning flux produced by the soldering and only a board passed the incircuit test is subjected to a function test at subsequent step S6 and a board passed the test is shipped (step S7).
Otherwise, the process goes to step S8 after step S1 where the electronic parts 31 are mounted by being inserted into mounting sections including parts mounting through holes, thereafter the electronic parts 31 are soldered using a solder reflow vessel at step S9, subjected to an incircuit test at step S10 and only a board passed the test is subjected to a function test at subsequent step S11 and only a board passed the test is shipped (S7).
FIG. 20 is an outward appearance perspective view of an incircuit tester used at steps S5 and S10 and shows the main portion of prior art board electrical-test probes in cross section and FIG. 21 is an enlarged view of the main portion thereof.
In FIG. 20 and FIG. 21, a plurality of probes 4 are arranged such that the contact pins 5 thereof are positioned to the solder fillets at the extreme ends of QFP (quad flat package) leads mounted to the printed circuit board 30. The probes 4 execute the incircuit test (steps S5 and S10 in FIG. 19), after electronic parts are mounted, by maintaining electric conductivity by moving the contact pins 5 upward or downward so that they are abutted against the solder fillets at the extreme ends of the QFP leads of a quad flat package (QFP) as an IC package.
Recently, as a surface mount density is increased, since it becomes difficult to obtain a space for disposing test pads to which the contact pins 5 of the test probes 4 are dropped, the test contact pins 5 cannot help being dropped to a limited region where flux F is thickly left when solder flows over and over again, the region corresponding to the solder fillet portion at the extreme end of the lead of the QFP package, the solder fillet portion of the soldering land portion (not shown) of chip parts and the like. As a result, since the flux F is still more deposited than ever at the extreme end of the test contact pin 5 as shown in FIG. 21, conductivity failure is liable to occur when the incircuit test is carried out.
The occurrence of the conductivity failure is characterized in that when the conductivity failure occurs once, although the flux F may be removed by repeatedly dropping the contact pin 5 twice or thrice, the method of removing the flux F by moving the contact pin many times cannot be employed because it is unstable. Thus, when the conductivity failure occurs once, parts which must be intrinsically accepted because no soldering failure and no device failure occurs to them are erroneously rejected.
As a result, the efficiency of a production line is greatly lowered. It is an ordinary practice to cope with this problem that when failure which seems to be caused by the dirt deposited to the extreme ends of the contact pins 5 often occurs, the contact pins 5 are directed upward by turning an upper plate 10 on which test probes 4 are disposed about 180.degree. in the direction of an arrow K and the flux F deposited to contact pins in the vicinity of the portion where the failure occurs is cleaned with a brush or the like and then the test is resumed. In addition, as to the contact pins 5 disposed to a lower plate 11, the flux F deposited to contact pins in the vicinity of the portion where failure occurs is cleaned with the brush or the like likewise.